This application is related to U.S. patent application Ser. No. 10/715,631, filed Nov. 18, 2003 and entitled “Low-Noise Filter for a Wireless Receiver”, and to U.S. patent application Ser. No. 10/725,767, filed Dec. 2, 2003, and entitled “DC Offset Cancellation in a Wireless Receiver”, both of which are incorporated herein by reference.
The field of the present invention is electronic circuits for active filtering. More particularly, the present invention relates to low-noise filters.
Wireless communication systems generally transmit a modulated radio frequency (RF) signal that is converted to a baseband signal in a receiver. A conventional receiver does this conversion in a two-stage process. In a first stage, the RF signal is down converted to an intermediate frequency (IF) signal, and then in a second stage, the IF signal is further down converted to the baseband frequency. This process enables simplified filtering and processing, but the two-stage architecture consumes valuable space and power in wireless devices. Accordingly, a newer single-stage architecture is being deployed. This single-stage architecture converts the RF signal directly to the baseband signal, and is typically referred to as direct conversion receiver (DCR) structure. As an alternative, some of the benefits of the DCR structure may be realized using a low IF architecture, while retaining some of the simplified filtering and processing of the IF structure. A low IF receiver converts a radio frequency (RF) signal to an intermediate frequency that is lower than the IF of a convention receiver.
The direct conversion receiver downconverts a radio frequency (RF) signal directly to baseband (DC) without first converting the RF signal to an intermediate frequency (IF). One of the benefits of a direct conversion receiver is the elimination of costly filter components used in systems that employ an intermediate frequency conversion. For example, in a conventional code division multiple access (CDMA) communication system, one or more surface acoustic wave (SAW) filters are implemented to aid in filtering the desired channel. To further complicate the circuitry, these SAW filters are typically located on a different device (i.e., “off-chip”) than many of the receiver components.
A low IF or a direct conversion receiver allows the filter components to be implemented using electronic circuitry that can be located on the same device (i.e., “on-chip”) as many of the receiver components. In a direct conversion receiver implementation, high-order (e.g., fifth-order or higher) active filters are used to attenuate the interferers before the baseband chip. Unfortunately, because the filters are implemented using electronic circuitry on the same chip as the receiver components, the filters add significant noise to the received signal. The added noise reduces the sensitivity of the receiver, thereby making such an active filter challenging to implement.
Noise contributed by a filter to the received signal can be defined by the equation Noise=kT/C (Equation 1), where k is a constant, T=temperature, and C=capacitance. From equation 1 it is clear that the noise is inversely proportional to the capacitance. To reduce the noise, the capacitance values are typically made large. Unfortunately, increasing the capacitance consumes valuable area on the integrated circuit (IC) on which the receiver is fabricated. The space required for these capacitors substantially increases the overall size for the receiver IC, as the filter capacitors typically represent the largest block on the IC.
When implementing a low IF or a direct conversion receiver, there is typically some amount of offset (referred to as “DC offset”) that appears on the downconverted baseband signal. The DC offset occurs due to filter or front-end mismatch and also due to self-mixing that can occur with the local oscillator (LO) signal, the radio frequency (RF) signal or interfering signals in the receiver. Typically, filter and front-end mismatch due to temperature change over time results in static DC offset. Self-mixing among the LO, RF and interfering signals, as well as reflection at the antenna, temperature variation and LO leakage result in dynamic DC offset. Correction for DC offset is typically performed on the baseband amplifier located in the receiver. Many techniques have been proposed to minimize DC-offset. For example, it is possible to minimize DC offset using digital calibration techniques in the analog-to-digital converter (A/D) located in the receiver. Alternately, sampling techniques and Sample-and-Hold (S/H) circuits have been used to subtract the estimated offset of the variable gain amplifier from the received signal.
Unfortunately, one or all of these techniques can only be applied to a system in which the receiver does not continuously operate, such as in a TDMA communication system. In a CDMA system, these techniques will not be effective because the receiver works continuously with no interruption. Furthermore, DC-offset correction using so called “auto-zeroing” techniques during start-up is not practical in a CDMA system because of dynamic offsets. In a CDMA system the only option that shows promise is the implementation of a so called “servo-loop” like architecture around the variable gain amplifier.
In a servo-loop architecture, the high pass cut-off frequency is dependent upon the gain characteristics of the variable gain amplifier and the amplifiers in the servo-loop. Because the transconductance of the variable gain amplifier varies significantly with the applied gain control signal (usually above 50 dB of range), the cut-off frequency varies by more than 50 dB, which places the cut-off frequency at a point at which data carried in the received signal will likely be lost. It is possible to adjust the high pass cut-off frequency by varying the gain of the amplifiers in the servo-loop inversely proportional to the transconductance amplification of the VGA. Since the transconductance amplification of the VGA varies proportionally to the exponential of the control voltage, the amplification of the amplifiers in the servo-loop must vary with the inverse of the exponential of the control voltage. Unfortunately, such a servo-loop increases significantly the complexity, power consumption and the area on the device occupied by the architecture.
Therefore, it would be desirable to minimize the amount of noise contributed to a received signal by filter components in a direct conversion receiver, while maximizing receiver sensitivity. It is also desirable to minimize the amount of area on a device consumed by the filter components, especially capacitor devices. It would also be desirable to efficiently provide DC offset cancellation in a wireless receiver operating in a communication system in which the receiver operates continuously.